1. Field of the Invention
The present invention relates to a method of forming a shallow junction and a semiconductor device having the shallow junction, and more particularly, it relates to a method of forming a shallow junction in a semiconductor device which has a silicon layer having a thin depth and a high concentration of impurities, and a semiconductor device, e.g., a bipolar transistor and a MOS transistor, having a shallow junction.
2. Description of the Related Art
In general, in a semiconductor device a semiconductor element is formed by providing an impurity diffusion layer in a semiconductor substrate. The impurity diffusion layer is provided by forming, for example, an SiO.sub.2 film, on a surface of a semiconductor substrate by a thermal oxidation method, patterning the SiO.sub.2 film by photolithography technology, and carrying out a selective thermal-diffusion of impurities or an ion-implantation using the SiO.sub.2 film as a mask.
The thermal diffusion process, however, comprises an annealing step at a high temperature, and thus impurities are diffused not only in the depth direction but also in the width direction. Consequently, it is difficult to control the diffusion of the impurities only in the depth direction. Particularly, when for example, an impurity having a large diffusion coefficient, for example, boron (B), is diffused, the impurity diffusion in both the width and depth directions is large, and thus a shallow junction can not be easily formed.
In the ion implanting process, the annealing process required for activating impurities and recovering damage takes a long time, thereby causing a redistribution of the implanted ions and the occurrence of a channeling phenomenon due to a particular crystalline orientation. Consequently, it is also difficult to form a shallow junction by ion-implantation, as it is in the above-mentioned thermal diffusion process.
Further, to reduce the channeling an ion-implanting process wherein ions are implanted at an angle of 7.degree. from the vertical is well known. A shallow portion is still formed, however, near the step portion, for example, the gate electrode portion, and thus it is difficult to stably form an impurity diffusion layer having a depth of 0.1 .mu.m (1000 .ANG.) or less by a conventional thermal diffusion process or ion implanting process.
Conventional examples, e.g., an npn type bipolar transistor having a base region having a high impurity, concentration, i.e., 1.times.10.sup.18 to 1.times.10.sup.21 cm.sup.-3, and a short channel type FET having an LDD (lightly doped drain) to prevent hot carrier effects, will be explained.
First, a conventional npn bipolar transistor and the production process therefor will be explained with reference to FIG. 1.
As shown in FIG. 1, an n.sup.+ type buried layer 2 is formed on a p type semiconductor substrate 1, and an n type semiconductor layer 3 acting as a collector is formed thereon.
Subsequently, a p.sup.+ type isolation semiconductor layer 4 is formed.
Then, for example, boron ions, are implanted only into a base formation region using a resist mask (not shown) having an opening thereat, to form a base 5, and subsequently, for example, arsenic ions, are implanted into an emitter formation region using a resist mask having an opening thereat to form an emitter 6. In FIG. 1, 8 is a field insulating film and C, B and E are a collector electrode, a base electrode, and an emitter electrode, respectively.
The electric properties of the semiconductor device are represented as follows. ##EQU1## wherein .beta. is a base transportation efficiency, W.sub.B : base layer thickness, L.sub.nB : base diffusion length, h.sub.FE : emitter ground current amplification ratio, .gamma.: emitter implanting efficiency, and f.sub..gamma. : cut off frequency. Equation (a) shows that, when the base layer thickness W.sub.B is narrowed, the base transportation efficiency .beta. becomes large, and equation (b) shows that, when the base transportation .beta. becomes large, the emitter ground current amplification ratio h.sub.FE becomes large. Further, equation (c) shows that, when the base layer thickness W.sub.B is narrowed, the cut off frequency f.gamma., which represents an operating frequency limit of a transistor, becomes high. Therefore, it is very important to narrow the base layer thickness W.sub.B to improve the properties of a semiconductor. A decrease of the ion implanting acceleration energy for impurity ions has been considered as a method of narrowing the base layer thickness W.sub.B, but in this case, channeling occurs, and as shown in FIG. 2 by a curve p, the base layer thickness is diffused into the inner portion of a semiconductor substrate. Therefore, to form a base layer having a thickness of 2000 to 3000 .ANG. or less is difficult in practice. The curves Q and R show the impurity concentration distribution in an emitter region and a collector region, respectively.
Next, a conventional FET having LDD will be explained with reference to FIG. 3.
In FIG. 3, 11 is an n type silicon layer such as an n type silicon substrate or n type silicon epitaxial layer, etc., 12 an SiO.sub.2 layer acting as an isolation region, 13 a gate insulating film having a thickness of 200 .ANG. , e.g., an SiO.sub.2 layer, 14 a gate electrode of polycrystalline silicon layer, 16 and 17 p.sup.+ source and drain regions, and 18 and 19 p.sup.- regions having an LDD.
Since the voltage used in a semiconductor device is generally constant, regardless of the size of the element, the carrier speed is increased near a drain region in a short channel FET, and a hot carrier effect is generated, and thus the insulation between a gate electrode and a drain might be broken. This phenomenon is particularly remarkable in an n channel type FET having electron carriers, but the same phenomenon can be recognized even in a p channel type FET.
The above-mentioned LDD was developed to prevent the hot carrier effect. Namely, as shown in FIG. 3, a low impurity concentration region (LDD) 19 is formed between a drain 17 and channel to lower the electric field strength, and thus prevent the hot carrier effect.
Although the LDD region preferably has a thickness of 1000 .ANG. or less, i.e. is thin when boron arsenic, and phosphorus, etc., are ion-implanted to form the LDD region, an LDD region having a thickness of 2500 .ANG. or less can not be easily formed due to the channelling, etc. The LDD region can be also formed by forming a boron oxide film using a thermal CVD process or plasma CVD process except for an ion implanting process and carrying out a heat treatment.
When using the thermal CVD process, however, a stacking fault is generated, and when using the plasma CVD process, etching rate of BSG is smaller than that of SiO.sub.2, and thus the process is not improved.